Recently,the Design Automation Conference (DAC 2026), a top conference in thefield of electronic design automation (EDA), announced the list ofaccepted papers. The team led by Professor Niu Dan from the schoolmade new progress in the bottleneck of core-particle heterogeneousintegration and high-bandwidth memory (HBM) design simulationacceleration. Three papers were accepted by the top internationalconference in the EDA field. The related work was supported by theNational Youth Talent Program, the National Key Research andDevelopment Program, the National Natural Science Foundation of ChinaKey and General Projects, and the Jiangsu Province Outstanding YouthProgram.
DACconference is known as "Oscar" of EDA, andis the only CCF-A conference in the EDA field,hosted by the American electronics association(ElectronicDesignAutomationConsortium), hasbeen held for 63 editions,featuringmore than 300 technical presentations each year.It is the largest, most influential and longest-standing topconference in the EDA field. Some of the papers are presented below:
Paper1: Construction and Simulation Algorithms for modular andReconfigurable core-grain heterogeneous Integrated thermal models
Thermalmanagement is crucial for the reliability of core-grain heterogeneousintegrated circuits in the post-Moore era. The design processrequires hundreds of thermal simulations under different powerdistributions, cooling conditions, and structural configurations.Traditional methods based on finite element methods (FEM) and compactthermal models (CTM) lack flexibility, cannot perform efficientmulti-scenario evaluations, and generate excessive computationalcosts when modeling complex vertical stacks with cross-scaleinterconnections. We propose LegoTherm, a modular thermal modelingframework that decomposes core-grain-based systems into reusablereduced-order components. The framework takes advantage of theinherent hierarchical structure of heterogeneous integrations toconstruct high-fidelity three-dimensional meshes through modulardiscretization, capture the details of micro-interconnects, and thengenerate reduced-order modules by aggregating thermally coupledports. This approach maintains the accuracy of key hotspots whileenabling rapid reassembly for different design scenarios. Inindustrial-grade 2.5D and 3D package benchmark tests, LegoTherm wasup to 10.39 times faster than commercial COMSOL while maintaining anaverage relative error of less than 0.40%. The framework shortens thecore-thermal design iteration cycle from weeks to half a day,addressing a key bottleneck in core-thermal design.
Paper2: An Accelerated Architecture for High-performance Sparse LUDecomposition Based on Asynchronous Task-Triggered HBM
SparseLU decomposition, as a core computing operator in fields such asscientific computing, circuit simulation, and linear circuit systemanalysis, directly affects the simulation speed of large-scalecomplex systems in terms of its execution efficiency. Although FPGAswithintegrated high-bandwidth memory (HBM) offer extremely high potentialfor concurrent access to handle such memory-intensive tasks,traditional hardware architectures still face severe challenges whendealing with the inherent and irregular data dependencies in sparsecomputing. Existing acceleration schemes are often constrained byrigid hierarchical synchronization mechanisms, resulting insignificant synchronization overhead and idle computing resources,and centralized schedulers can easily become performance bottleneckswhen dealing with large-scale parallel tasks. To break through theseperformance limitations while maintaining computational accuracy, wepropose SALUT, a novel HBM FPGA sparse LU decomposition accelerationframework based on asynchronous task-triggered. At the core of theapproach lies the development of an asynchronous task activationmechanism that transforms complex runtime data dependency resolutioninto fine-grained segment-level dependency management throughprecompilation techniques, thereby eliminating redundant waitingprocesses in traditional column-level synchronization. At thehardware architecture level, SALUT achieves deep decoupling of taskactivation and dependency resolution, combined with a locality-awaredual-queue load balancing strategy, maximizing the utilization ofprocessing units while ensuring a high cache hit rate. The algorithmdemonstrated outstanding performance in 15 real sparse matrix tests,achieving up to 4.0 times throughput improvement and 6.5 times energyefficiency improvement compared to NVIDIA's cutting-edge librarycuDSS (based on RTX A6000 GPU), and even compared to Tesla V100 GPU,italso achieved 3.7 times performance and a 4.7ximprovement in energy efficiency,respectively. The proposed SALUT model significantly reducesprocessing latency in irregular computations through asynchronousstream scheduling, achieving a qualitative change in the speed ofsubsequent large-scale system simulations.
Asthe "crown jewel" supporting the trillion-yuansemiconductor industry and one of the key bottlenecks restricting thedevelopment of the semiconductor industry in the post-Moore era, EDAtools have become a must-win territory in the increasingly fiercecompetition of the global semiconductor industry and will also be thetop priority of the national development strategy. In EDA, fast andaccurate large-scale circuit simulation technology will be the keycore to support the intelligent and agile design of analog and hybridintegrated circuits in the post-Moore era. In recent years, ProfessorNiu Dan's team has focused on the intersection of artificialintelligence and large-scale integrated circuit design and simulationacceleration and proposed a series of optimization strategies, Morethan 30 papers have been published in top international conferencesand journals in EDA or artificial intelligence, such as DAC, ICCAD,DATE, IEEE TCAD, IEEE TC, CVPR, AAAI, ICCV. In terms of application,the team has extensive industry-university-research cooperation withseveral leading domestic EDA companies, applying algorithmic researchresults in the industrial field and providing core algorithmicsupport for customers in a series of important chip designverification links such as large-scale integrated circuit generation,DC analysis, transient analysis, and core-particle electrothermalsimulation.
